This invention is related to adders for the arithmatic logic unit (ALU) of a computer.
An adder is an important element in an arithmatic logic unit (ALU). Two n-bit input data and carry data can produce (n+1) bit sum output. In an ALU, the adder is often accompanied with a "zero-flag" generator to determine whether the sum output of the most significant bit is zero or not for activating other related control circuits. A conventional zero-flag generator, as shown in FIG. 1, is composed of a group of NOR logic gates. As shown in this figure, the data inputs Din.sub.-- a and Din.sub.-- b are summed with the carry signal CIN of a previous stage in an adder. For the (n-1)th bit, the sum output cannot be determined until the output of the least significant bit is rippled through all the intermediate bits to reach the (n-1)th bit. The adder has a sum output OVF and a carry output Co, which are fed to the terminals WE.sub.-- v and WE.sub.-- c respectively. Besides, another output is fed to a zero-flag generator A=0? to determine whether the sum is zero or not. If the sum is zero, a zero-flag signal appears on line Z and is fed to terminal WE.sub.-- Z.
In this process, the zero-flag signal is generated after an adder has produced a result, and is not predicted ahead of time. Thus, the processing speed is slow without the "zero look ahead" feature. Only one relative solution to this problem is disclosed in the U.S. Pat. No. 4,878,189. In this patent, the arithmatic logic unit (ALU) is executed for addition function. The patented circuit belongs to traditional implementation methods, in that there is delay of the critical path in the design of the central processing unit (CPU).